hv748 features hvcmos technology for high performance high density integration ultrasound transmitter 0 to 75v output voltage 1.25a source and sink current in pulse mode 400ma source and sink current in cw mode up to 20mhz operating frequency matched delay times 1.2v to 5.0v cmos logic interface built-in output drain bleed resistors application portable medical ultrasound imaging piezoelectric transducer drivers ndt ultrasound transmission pulse waveform generator ? ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex hv748 is a four-channel, monolithic, high voltage, high speed pulse generator. it is designed for portable medical ultrasound applications. this high voltage and high speed integrated circuit can also be used for piezoelectric, capacitive or mems sensing in ultrasonic nondestructive detection and sonar ranger applications. the hv748 consists of a controller logic interface circuit, level translators, mosfet gate drives and high current power p- channel and n-channel mosfets as the output stage for each channel. the output stages of each channel are designed to provide peak output currents over 1.8a for pulsing, when in mode 4, with up to 75 volt swings. when in mode 1, all the output stages drop the peak current to 400ma for low-voltage cw mode operation to decrease the power consumption of the ic. the p and n type of power fets gate drivers are supplied by two ? oating 9.0vdc power supplies reference to v pp and v nn . this direct coupling topology of the gate drivers not only eliminates two high voltage capacitors per channel, but also makes the pcb layout easier. typical application circuit quad high speed 75v 1.25a ultrasound pulser nin1 sub v pp - 9v v pf v dd +9v g ref +1.8 to 3.3v logic v pp 0 to +75v en mc1 c1 v nn 0 to -75v txn1 v nn + 9v 1 of 4 channels c2 c3 c5 c4 txp1 hv out 1 x1 d1 d2 v nf v sub v ll +1.8 to 3.3v +75v c6 c7 en_pwr mc0 otp v ss pin1 r p1 r n1 rgnd hv748 level translator rgnd p-driver n-driver level translator
2 hv748 ordering information device package options 48-lead qfn 7x7mm body, 1.0mm height (max), 0.5mm pitch hv748 HV748K6-G -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v ss , power supply reference 0v v ll , positive logic supply -0.5v to +7.0v v dd , positive logic and level translator supply -0.5v to +14v (v pp -v pf ) positive ? oating gate drive supply -0.5v to +14v (v nf - v nn ) negative gate ? oating drive supply -0.5v to +14v (v pp -v nn ) differential high voltage supply +170v v pp , high voltage positive supply -0.5v to +85v v nn , high voltage negative supply +0.5v to C85v otp, over temperature protection output -0.5v to +7.0v all logic input pin x , nin x and en voltages -0.5v to +7.0v (v sub - v ss ) substrate to v ss voltage difference +170v (v pp Ctxp x ) v pp to txp x voltage difference +170v (v sub - txp x ) substrate to txp x voltage difference +170v (txn x -v nn ) txn x to v nn voltage difference +170v operating temperature -40c to 125c storage temperature -65c to 150c thermal resistance, ja 29c/w thermal resistance, jc (junction to thermal pad) 0.5c/w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. power-up sequence 1v sub 2v ll with logic signal low 3v dd 4(v pp -v pf ) and (v nf Cv nn ) 5v pp and v nn 6 logic control signals power-down sequence 1 all logic signals go to low 2v pp and v nn 3(v pp -v pf ) and (v nf Cv nn ) 4v dd 5v ll 6v sub pin con? guration 1 48 48-lead qfn (top view) package marking l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = green packaging hv748k6 lllllllll yyww aaa ccc 48-lead qfn
3 hv748 operating supply voltages and current (4 channel active) (operating conditions, unless otherwise speci? ed, v ss = 0v, v ll = +2.5v, v dd = +9.0v, v pp -v pf = +9.0v, v nn -v nf = -9.0v, v pp =+75v, v nn = -75v, t a = 25c) symbol parameter min typ max units conditions v ll logic voltage reference 1.2 1.8 to 3.3 5.0 v --- v dd internal voltage supply 8.0 9.0 12 v --- v pf positive gate driver supply (v pp -12) (v pp -9.0) (v pp -8.0) v floating driver voltage supplies. v nf negative gate drive supply (v nn +8.0) (v nn +9.0) v v sub ic substrate voltage v dd v pp +75 v must be the most positive potential of the ic. v pp positive hv supply 0 - +75 v --- v nn negative hv supply -75 - 0 v --- sr max slew rate limit of v pp , v nn - - 25 v/s built-in slew rate detection protection. i ll v ll current en = low - 35 120 a --- i ddq v dd current en = low - 15 - a --- i dden v dd current en = high - 0.75 2.0 ma f = 0mhz i dden v dd current mode = 4 - 0.75 - ma f = 5.0mhz, continuous, no loads i ddencw v dd current mode = 1 - 2.0 - ma i ppq v pp current en = low - 10 25 a f = 0mhz i ppen v pp current mode = 4 - 250 - ma f = 5.0mhz, continuous, no loads i ppencw v pp current mode = 1 - 170 - ma i nnq v nn current en = low - 15 30 a f = 0mhz i nnen v nn current mode = 4 - 250 - ma f = 5.0mhz, continuous, no loads i nnencw v nn current mode = 1 - 170 - ma i pfq v pf current en = low - 10 25 a f = 0mhz i pfen v pf current mode = 4 - 50 - ma f = 5.0mhz, continuous, no loads i pfencw v pf current mode = 1 - 12 - ma i nfq v nf current en = low - 20 30 a f = 0mhz i nfen v nf current mode = 4 - 25 - ma f = 5.0mhz, continuous, no loads i nfencw v nf current mode = 1 - 12 - ma note: all supply current values are for reference only. under voltage and over temperature protection symbol parameter min typ max units conditions v pull_up open drain pull-up voltage - - 5.0 v --- v uvdd v dd threshold 4.5 - 6.0 v --- v uvll v ll threshold 0.8 0.9 1.0 v --- v uvvf v pf , v nf threshold 4.5 - 6.0 v --- v ol_otp otp ? ag output low voltage - - 1.0 v v ll = 3.3v, otp = active, i pull_up = 1.0ma. i otp max. open drain output current - 1.0 - ma --- t otp over-temperature threshold 95 110 125 c if over-temperature occurred, otp low and all tx outputs will be hiz. t hys otp output reset hysteresis - 7.0 -
4 hv748 electrical characteristics (operating conditions, unless otherwise speci? ed, v ss = 0v, v ll = +3.3v, v dd = +9v, v pf = v pp -9v, v nf = v nn + 9v, v pp = +75v, v nn = -75v, t a = 25c) output p-channel mosfet, txp (mode 4) symbol parameter min typ max units conditions i out output saturation current 1.25 1.8 - a --- r on channel resistance - 8.0 - i sd = 100ma c oss output capacitance - 100 - pf v ds = 25v, f = 1.0mhz output n-channel mosfet, txn (mode 4) symbol parameter min typ max units conditions i out output saturation current 1.25 1.8 - a --- r on channel resistance - 7.5 - i sd = 100ma c oss output capacitance - 40 - pf v ds = 25v, f = 1.0mhz mosfet drain bleed resistor symbol parameter min typ max units conditions r p/n1~4 output bleed resistance 10 15 20 k --- p ro bleed resistors power limit - - 40 mw --- logic inputs symbol parameter min typ max units conditions v ih input logic high voltage (v ll -0.4) - v ll v --- v il input logic low voltage 0 - 0.4 v --- i ih input logic high current - - 10 a --- i il input logic low current -10 - - a --- c in input logic capacitance - - 5.0 pf --- ac electrical characteristics (operating conditions, unless otherwise speci? ed, v ss =0v, v ll = +3.3v, v dd = +9v, v pf = (v pp - 9v), v nf = (v nn +9v), v pp = +75v, v nn = -75v, t a = 25c) symbol parameter min typ max units conditions t r output rise time - 35 - ns 330pf//2.5k load t f output fall time - 43 - ns f out output frequency range - - 20 mhz 100 resistor load hd2 second harmonic distortion - -40 - db t en enable time - 180 500 s t dis disable time - 2.8 10 s t dr delay time on inputs rise - 22 - ns t df delay time on inputs fall - 22 - ns t dm delay on mode change - 2.5 10 s t delay |t dr - t df | delay time matching - 2.0 - ns p to n, channel to channel t j delay jitter on rise or fall - 15 - ps v pp /v nn = 25v, input t r 50% to hv out t r or t f 50%, with 330pf//2.5k load
5 hv748 switching time diagram truth table (all modes) logic inputs output en pin x nin x txp x txn x 100offoff 1 1 0 on off 101offon 111on*on* 0 x x off off *note: not allowed, may damage ic t dr 50% 10% 50% 90% pinx ninx t df output v nn v pp t r 10% t f 90% 0 drive mode control table mode mc1 mc0 i sc (a) r onp () r onr () 1 0 0 0.41 35 33 2 0 1 0.58 25 23 3 1 0 0.97 15 14 4 1 1 1.8 8.0 7.5 *note: 1.v pp /v nn = +/-75v, v dd = (v pp C v pf ) = (v nf C v nn ) = +9.0v 2. i sc is current into 1.0 to gnd 3. r on calculated from v out into 100 load
6 hv748 pin # name function 1, 12 v dd positive internal voltage supply (+9.0v). 2, 11 v ss power supply return (0v). 48 v ll logic hi voltage reference input (+3.3v). 47 g ref logic low reference, logic ground (0v). 26, 35 rgnd bleed resistors common return ground. (both pins must be used). 18, 19, 20, 41, 42, 43 v pp positive high voltage power supply (+75v). 21, 22, 23, 38, 39, 40 v nn negative high voltage power supply (-75v). 17, 44 v pf p-fet drive ? oating power supply, (v pp - v pf ) = +9.0v. 24, 37 v nf n-fet drive ? oating power supply, (v nf - v nn ) = +9.0v. 34 txp1 output p-fet drain (open drain output) for channel 1. 33 txn1 output n-fet drain (open drain output) for channel 1. 32 txp2 output p-fet drain (open drain output) for channel 2. 31 txn2 output n-fet drain (open drain output) for channel 2. 30 txp3 output p-fet drain (open drain output) for channel 3. 29 txn3 output n-fet drain (open drain output) for channel 3. 28 txp4 output p-fet drain (open drain output) for channel 4. 27 txn4 output n-fet drain (open drain output) for channel 4. 3 pin1 input logic control of high voltage output p-fet of channel 1, hi=on, low=off. 4 nin1 input logic control of high voltage output n-fet of channel 1, hi=on, low=off. 5 pin2 input logic control of high voltage output p-fet of channel 2, hi=on, low=off. 6 nin2 input logic control of high voltage output n-fet of channel 2, hi=on, low=off. 7 pin3 input logic control of high voltage output p-fet of channel 3, hi=on, low=off. 8 nin3 input logic control of high voltage output n-fet of channel 3, hi=on, low=off. 9 pin4 input logic control of high voltage output p-fet of channel 4, hi=on, low=off. 10 nin4 input logic control of high voltage output n-fet of channel 4, hi=on, low=off. 46 en chip power enable hi=on, low=off. 15 mc0 output current mode control pins, see drive mode control table. 14 mc1 13 otp over temperature protection output, open n-fet drain, active low if ic temperature >110c. 16, 25, 36, 45 thermal pad (v sub ) substrate of the ic, substrate bottom is internally connected to the central thermal pad on the bottom of package. it must be connected to v sub , the most positive potential of the ic externally. pin description
7 hv748 (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv748 nr060807 48-lead qfn package outline (k6) 7x7mm body, 1.0mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 6.85 2.25 6.85 2.25 0.50 bsc 0.30 0.00 0 o nom 0.90 0.02 0.25 7.00 4.70 7.00 4.70 0.40 - - max 1.00 0.05 0.30 7.15 5.25 7.15 5.25 0.50 0.15 14 o jedec registration mo-220, variation vkkd-2, issue k, june 2006. drawings are not to scale. notes: details of pin 1 identi? er are optional, but must be located within the indicated area. the pin 1 identi? er may be either a m old, or an embedded metal or marked feature. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. the inner tip of the lead may be either rounded or square. 1. 2. 3. seating plane top view side view bottom view a a1 d e d2 b e2 a3 l l1 view b view b 1 note 3 note 2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) e 48 1 48
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